Consider the function $f=a(b\frac{+}{b}ar(d))+(\frac{?}{\text{b}\text{a}\text{r}}(c)(\frac{?}{\text{b}\text{a}\text{r}}(bo+d))\frac{+}{b}ar(b)\frac{c}{b}ar(d)).\backslash$table$[[$Gate$,$Number of Transistors,t$\_($cd$),$t$\_($pd$)],[$NOT$,2,0\mathrm{.}4,0\mathrm{.}5],[$AND$2,6,2\mathrm{.}2,2\mathrm{.}6],[$OR$2,6,2\mathrm{.}2,2\mathrm{.}6],[$NAND$2,4,1\mathrm{.}8,2\mathrm{.}1],[$NOR$2,4,1\mathrm{.}8,2\mathrm{.}1],[$XOR$2,8,2\mathrm{.}6,3\mathrm{.}2],[$XNOR$2,8,2\mathrm{.}6,3\mathrm{.}2]]($b$)$ Give an implementation of $f$ that minimizes, in order of highest to lowest priority, the number of

transistors, the critical path length, and then the short path length. Only use the gates listed in the

gate table. $($c$)$ Compute the transistor count, critical path length, and short path length of your implementation in

the previous part.$($d$)$ Label each wire in your schematic and trace the signal timing when abcd$=1100$ transitions to

abcd$=1000.$

$(a)$ Find the sum$-of-$product expression for $f$ with $as$ few literals $as$ possible.

$(b)Givean$ implementation $off$ that minimizes, $in$ order $of$ highest $to$ lowest priority, the number $of$ transistors, the critical path length, and then the short path length. Only use the gates listed $in$ the gate table.

$(d)$ Label each wire $in$ your schematic and trace the signal timing when abcd $=1100$ transitions $to$ abcd $=1000.$