Consider the given below SystemVerilog implementation of full$-$adder circuit using half adder $($half$\_$addr$)$ instances :

Consider the half$\_$addr module has inputs ports $$x$$ and $$y$$ and output ports $$sum$$ and $$carry$$

module fa$($input logic x$,$ y$,$ cin

$$output logic sum,cout$)$;

$$

$$logic temp$\_$carry$0,$ temp$\_$sum, temp$\_$carry$1$;

$$

$$half$\_$adder h$0(.$x$(\_\_($i$)\_\_),$

$.$y$($y$),$

$.$c$(\_\_($ii$)\_\_),$

$.$s$($temp$\_$sum$))$;

$$

$$half$\_$adder h$0(.$x$($temp$\_$sum$),$

$.$y$($cin$),$

$.$c$($temp$\_$carry$1),$

$.$s$($sum$))$;

$$

$$assign cout $=$ temp$\_$carry$0|$ temp$\_$carry$1$;

endmodule

Select the appropriate port connections in half adder instance h$0($i$)$ and $($ii$).$

Hint: Refer to lecture slides to understand how full$-$adders can be designed with half$-$adder.

Question $29$ options:

$($i$)$ x $($ii$)$ temp$\_$carry$0$

None of the others

$($i$)$ temp$\_$carry$0($ii$)$ cin

$($i$)$ cin$($ii$)$ temp$\_$carry$0$

$($i$)$ x $($ii$)$ cin