Consider the pipeline with $5$ stages: IF$,$ ID$,$ EX$,$ M and W$.$ Assume that each stage requires one

clock cycle. Show how the following program segment for adding $2$ arrays is processed and compare the clock cycles needed in non$-$pipeline system with pipelined system when result of the branch instruction l$.$e$.$ content of is available after WB stage. LOAD R$4$ #$400$ L$1$: LOAD R$1,0($R$4)$; LOAD R$2,400($R$4)$;

ADD R$3,$ R$1,$ R$2$:

STORE R$3,0($R$4)$

SUB R$4,$ R$4,$ #$4$;

BNEZ R$4,$ L$1$;