Question: Consider the Verilog module shown below: module rand_num (input logic clk, rst, load, input logic [7:0] seed, output logic [7:0] va); always_ff @(posedge clk) begin

Consider the Verilog module shown below: module rand_num (input logic clk,

Consider the Verilog module shown below: module rand_num (input logic clk, rst, load, input logic [7:0] seed, output logic [7:0] va); always_ff @(posedge clk) begin if (rst) val8'b0; else if (load) val

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