Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI $($class A$,$ B$,$ C$,$ and D$).$ P$1$ with a clock rate of $3\mathrm{.}0GHz$ and CPIs of $3,2,1,$ and $4,$ and P$2$ with a clock rate of $2\mathrm{.}5GHz$ and CPIs of $2,2,2,$ and $2.$

Given a program with a dynamic instruction count of $1\mathrm{.}0E5$ instructions divided into classes as follows: $20\%$ class A$,40\%$ class B$,30\%$ class C$,$ and $10\%$ class D$,$