Create another module referred as test bench to verify the functionality.

Use Asynchronous reset or Synchronous reset CODE //BCD counter module p19(clk ,reset ,dout ); output [3:0] dout ; reg [3:0] dout ; input clk ; wire clk ; input reset ; wire reset ; initial dout = 0 ; always @ (posedge (clk)) begin if (reset) dout <= 0; else if (dout<=9) begin dout <= dout + 1; end else if (dout==9) begin dout <= 0; end end endmodule