CSC 3101 - Lab 7: A Counter that Jumps Using Logicly, design a circuit that counts from 0 to 7 on a display in order at every clock rising edge: display: 0 1 2 3 4 5 6 7 0 1 2... Required components to be used and designed: 1) 4-bit Full Adder (FA) that adds the state bits S to a 4-bits Boolean variable V, 2) 4-bit resettable register to store the FA result, 3) a control unit/decoder that takes as input the current state S and generates the required Carry in and the V bits for the FA. You should reset the register at the beginning to initialize the current state to 0. The adder should add +1 to the state bits until 7 is reached, at that point it should generate C_in=1 and V=1000 to transform the adder into a subtractor (effectively doing 7-7=0).

You can Starting with this circuit