(d) (15 points) Consider the following loop being executed by a dual issue cpu: Loop LD DAD DIU SD DAD DIU BNE R2, 0(R1) R2, R2, #1 R2,0 (R1) R1 , R1,#8 R2, R3, Loop List when each instruction, for the first three iterations of the loop lssues, Executes, Reads, Writes value onto CDB, and commits, assuming speculation. (15 Points) Assume sufficient FUs, a suffciently large reorder buffer, and that at most two instructions can commit in any clock cycle. Iter. Instruction IssuesExecutes Mem access Writes CDB Commits LD R2,0(R1) DAD DIU R2, R2, #1 SD R2,0(R1) DAD DI URI, R1, #8 BNE R2,R3, Loop 2 LD R2,0(R1) DAD DIU R2, R2, #1 2 SD R2,0(R1) DAD DI URI, R1, #8 2 BNE R2,R3,Loop 3 LD R2,0(R1) 3 DADDIU R2, R2, #1 3SD R2,0(R1) 3 | DAD DI URI, R1, #8 3BNE R2,R3,Loop (d) (15 points) Consider the following loop being executed by a dual issue cpu: Loop LD DAD DIU SD DAD DIU BNE R2, 0(R1) R2, R2, #1 R2,0 (R1) R1 , R1,#8 R2, R3, Loop List when each instruction, for the first three iterations of the loop lssues, Executes, Reads, Writes value onto CDB, and commits, assuming speculation. (15 Points) Assume sufficient FUs, a suffciently large reorder buffer, and that at most two instructions can commit in any clock cycle. Iter. Instruction IssuesExecutes Mem access Writes CDB Commits LD R2,0(R1) DAD DIU R2, R2, #1 SD R2,0(R1) DAD DI URI, R1, #8 BNE R2,R3, Loop 2 LD R2,0(R1) DAD DIU R2, R2, #1 2 SD R2,0(R1) DAD DI URI, R1, #8 2 BNE R2,R3,Loop 3 LD R2,0(R1) 3 DADDIU R2, R2, #1 3SD R2,0(R1) 3 | DAD DI URI, R1, #8 3BNE R2,R3,Loop