Design $8-$bit Serial Adder with Accumulator using components of full adder, D$-$FF$,$ serial adder control circuit, and $8-$bit shift register. The $8-$bit shift register has serial in$,$ shift right, load, and clock as one$-$bit inputs, d as $8-$bit input, and q as $8-$bit output. The main design has load, start, clock as one$-$bit inputs, a & b as $8-$bit inout. Please upload one file that includes the VHDL code as text, screen shots of RTL viewer & Technology map viewer, and simulation results.