Design a $4-$bit shift register that can $(1)$ shift its information at right, $(2)$ shift its information at left and $(3)$ asynchronously initialize to state $0000$ when RST$=1.$

The figure below shows the circuit inputs and outputs. $($Use exactly these names. Respect upper and lower case$)$:

clk: Input. Clock signal.

RST: Input. Reset signal.

N: Data input.

$,$ SL $($Shift$\_$Left$)$: Input. When SL$=1($and SR$=0),$ the information moves one position at left and IN inputs to the rightmost flip flop.

$SR($Shift$\_$Right$)$: Input. When SR$=1($and SL$=0),$ the information moves one position at right and IN inputs to the leftmost flip flop.

When $SR=SL=0$ or $SR=SL=1$ the information remains unchanged.

OUT: Output. It outputs the state of the rightmost flip flop.

Note $1$: When using multiplexers from the library, set the "Include Enable?" field to No to remove the "Enable" pin.

Note $2$: To properly verify the circuit, VerilUOC$\_$Desktop requires all inputs of the flip flops are connected to some value. In this case, $"$S$"$ inputs must be connected to

Click in "Wiring" $($left menu$),$ select "Constant" and, in the Value property replace the Ox$1$ by $0$x$0($this will set the constant to $0).$ Connect the resulting constant to

the $"$S$"$ inputs.