1. Design a code in Verilog HDL and create the symbol of the Register File (RF), for

MIPS-16 processor

In MIPS-16 bits, the R-type format is given as follow: OP (3-bits) Rs(3-bits) Rt(3-bits) Rd(3-bits) Funct(4-bits) A. Design a code in Verilog HDL and create the symbol of the Register File (RF), for MIPS-16 processor, as explained in figure below. And save random initial values inside the RF (use Verilog initial statement). Write enable (R$) - Read Read to (Rt) register 1 Read data 1 register 2 Registers Write Register Write Read to data 2 data Clock