Design a control unit of a simple processor to perform the operations mentioned in Table below. For the control unit,

a$)$ Develop the timing signals for the operations

b$)$ Tabulate the necessary control signals that needs to be asserted during the timings of a$)$

c$)$ Derive the expressions for all the control signals of b$).$

Where,

a$)$ Rx and Ry are the registers from R$0,$ R$1,$ R$2,$ R$3.$ All these registers are connected to a common bus through a tri$-$state buffer.

b$)$ External data can be loaded into these registers with a tri$-$state buffer.

c$)$ Use accumulator $($A$)$ and base register $($B$)$ for temporary operations with Arithmetic unit.

d$)$ Each operation begins upon the assertion of signal W to $1$

e$)$ Completion of each operation is indicated by asserting the signal Done $\backslash (=1\backslash )$

f$)$ Use control signal $\backslash ($ A d d $/\backslash$overline$\{$S u b$\}\backslash )$ to control the addition and subtraction operations.