Design a Mealy$-$type FSM $($using D Flip Flops$)$ to detect $11,$ that is$,$ once the input has the sequence $11,$ the output is $1$; otherwise, the output is $0.$ Please draw the FSM bubble diagram and resultant sequential circuit.

You need to use the four steps to synthesize the circuit.

$1)$ Generate an FSM bubble diagram;

$2)$ Convert the bubble diagram to a state table $($with digital sequences to represent the states$)$;

$3)$ Generate logic functions for outputs and next states based on truth tables or K$-$maps;

$4)$ Draw the schematic.