Question: Design a Moore FSM based sequence detector ( only state diagram and state table ) that can detect the sequence 0 , 1 , 1

Design a Moore FSM based sequence detector (only state diagram and state table) that can detect the sequence 0,1,1,0 or 1,0,1,1. The sequence detector should allow overlap. Write a VHDL code in Vivado that implements the described sequence detector. Clearly mark the start/reset state and use synchronous active high reset to reset the sequence detector.

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