Design a system that accepts as input a 1-bit input stream outputs 1 (forever) if it takes an even number of clock cycles to recognize all of the following patterns at least once: 011, 00- and 101. Otherwise, it outputs 0. Use at most 1 T-flip flop, JK-flip flops, AND, OR and NOT gates (all inputs, their complements, 0 and 1 are available). Examples: For input sequence 00101011, the output is 1, because all three patterns appear at least once, and the last recognized pattern (011) ends at the 8th clock cycle, which is an even number. Whereas stream 011000101 is not accepted since the last recognized pattern is ends at the 9th cycle. Therefore, all patterns must be seen at least once and the last pattern to be seen must finish on an even cycle.