Design an 8-bit successive approximation register (using VHDL) whose input is A>B. Test-it out by suecessively approximating A sueh that, after eight successive approximations, A B (as in the diagram above where the "operation" is A'). Write a test medule and show at least two examples. - Design an 8 bit successive approximation negieter Luering VHDL) whose inpuit in A>B. Teet it out by successively approximating it such thats after eight nceseive a approximations,"; ARB. Write a test module and share at least two examples. Design an 8-bit successive approximation register (using VHDL) whose input is A>B. Test-it out by suecessively approximating A sueh that, after eight successive approximations, A B (as in the diagram above where the "operation" is A'). Write a test medule and show at least two examples. - Design an 8 bit successive approximation negieter Luering VHDL) whose inpuit in A>B. Teet it out by successively approximating it such thats after eight nceseive a approximations,"; ARB. Write a test module and share at least two examples