Design an Arithmetic and Logic Unit (ALU) that will implement the following functions

on one or two of the two 8-bits input operands (X and Y) and produce the result of the operation in output (Z).

The following table indicates Operation the ALU should produce for the given value of the Control Inputs (C).

000	No-Op
001	Add X+Y
010	Sub X-Y
011	X and Y
100	X or Y
101	X xor Y
110	NOT X
111	NOT Y

<-Allow a Carry-in and be able to produce a Carry-out

Make Sure to provide Registers for holding the values for

X, Y, and Z, also provide one extra storage bit in the Z-Register

to store the Carry-out. For the Carry-in you should provide

to sources of one should be an ExtCarry-in, and the other

should be carry-out from a previous addition stored in the

Z-Carry bit.

Grading Criteria

Top-Level Block Diagram showing properly and mnemonically named inputs and outputs.

Detailed Block Diagram showing the blocks performing the different computations and how are these selected for out to the Z-register.

VHDL Model for every ALU function sub-block, and for the structured VHDL Model for the ALU combining these sub-models