Design FSM digital lock (4 digits) using Verilog code (EDAplayground). requirement: user input: 0-9 clear set lock standard input clock, rest default code :0000 output: red light green light bolt Final requirement create a FSM of the system by hand Model the FSM in Verilog/EDA Playground When entering a new code or attempting to enter the code to unlock the door, each of the four numbers is its own state Include your FSM and any other drawings you may have in the lab report Explain the process of your sequence of inputs, including the behaviors that it is mimicking and demonstrating that your system properly | responds to those inputs