Design Problem

Design a Mealy FSM that recognizes a nonempty input sequence in which the difference between the number of $0$ s and the number of $1$ s is a multiple of $3.$ While drawing Next State Logic and Output Logic circuits in the Mealy FSM Schematic, use three basic gates only $(2-$input AND gates, $2-$input OR gates, NOT gates$).$

Grading Criteria:

$1.$ State Transition Diagram

$2.$ Descriptions of States

$3.$ State Reduction $($if possible$)$

$4.$ State Transition & Output Table

$5.$ State Encoding

$6.$ State Transition & Output Table with State Codes

$7.$ K$-$Maps

$8.$ Simplified Expressions of Next State Bits & Output

$9.$ Mealy FSM Circuit Schematic

a$.$ Next State Logic Circuit

b$.$ Output Logic

c$.$ Rest of Schematic