Design Project $1$ for ECE $271$ is a group project assigned to teams of up to $3$ members. You may choose your groups only if you email the instructor TA list Monday of week $6$ with your team members cc$\text{'}$d using your OSU email addresses. If this is not completed you will randomly be put into groups Monday of week $6.$ Your team needs to pick one of the project options below and develop a logic that will accomplish the task. This project is intentionally kept small so you should accomplish this without the need of software tools like ModelSim or similar $($you may use them to confirm your design$).$ To complete the project, your team needs to submit a final PDF showing every step of the design process including any state diagrams, truth tables, KMaps$/$Logic Minimizations, logic diagrams, etc.. There also must be a one$-$page description of the solution describing any approaches taken, struggles encountered, and any interesting modification made.Options:$1.$ Serial TransmissionDesign a system that will take a $4$ bit wide input and send it bit by bit over a connection and reassemble it on the other side. This should likely be treated as two state machines, one to serialize the input and the second to reassemble it$.$ Some possible improvements could be to add compression, error detection, or to expand to $8$ or $16$ bits wide$\mathrm{.}2.$ Summation CalculatorDesign a system that given up to $4$ bit $($positive$)$ number will sum the value of that number and each lower value. For example a $3$ would return $3+2+1+0=6.$ Pay attention to how big numbers are so they do not overflow where you store them. This is likely made from a counter, an adder $($more than $4$ bits$),$ and some extra storage registers. Some possible improvements could be designs that compute in fewer steps or intentionally use fewer gates$/$smaller gates.