Question: Design, simulate and validate VHDL module for the first two key steps of the AES Encryption, SubBytes ( ) and ShiftRows ( ) . The

Design, simulate and validate VHDL module for the first two key steps of the AES Encryption, SubBytes() and ShiftRows(). The waveforms showing the results MUST include all your test cases.
Design, simulate and validate VHDL module for the first two key

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