Question: Design, simulate and validate VHDL module for the first two key steps of the AES Encryption, SubBytes ( ) and ShiftRows ( ) . in

Design, simulate and validate VHDL module for the first two key steps of the AES Encryption, SubBytes()and ShiftRows().in the VIVADO The waveforms showing the results MUST include all your test cases.
High-level Block diagrams for each module should be included, showing how 16-Byte registers and operators (MUX, Rotator, XOR, etc) in a module are connected.
Design, simulate and validate VHDL module for the first two key

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