Design Specification

In this lab, a synchronous sequential circuit is design to recognize a sequence of 11*0 where 1* represents any number of logic 1s, e.g., 0 logic 1, 1 logic 1, 2 logic 1s, .. The sequential circuit has one input I and one output Z, and Z outputs logic 1 when the machine identifies a sequence of 11*0. A sample input sequence and output response is given below.

I = 0 1 1 0 0 1 0 1 0 0 1

Z= 0 0 0 1 0 0 1 0 1 0 0

1) Major design steps, e.g., state diagram, state assignment, state table, FF-type selection (D-FFs), simplified FF input equations and output equation, logic diagram. Note that you MUST include the design steps in the pre-lab design report. This part has very high weighting in the grading.

2) Test patterns for the circuit.

3) Verilog codes (D_FF module, 11*0 detector module, and testbench) for ISE simulation or logicSim simulation.