Question: Design the reversible two bit counter using JK flip-flops with asynchronous clear and load. The counter is counting modulo 4 up and down for x

Design the reversible two bit counter using JK flip-flops with asynchronous clear and load. The counter is counting modulo 4 up and down for x =0 and for x=1, respectively. Please prepare report including coded state transition table, excitation tables and formulas

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