Question: Design the reversible two bit counter using JK flip-flops with asynchronous clear and load. The counter is counting modulo 4 up and down. Please prepare

Design the reversible two bit counter using JK flip-flops with asynchronous clear and load. The counter is counting modulo 4 up and down. Please prepare report including coded state transition table, excitation tables, formulas and schematic.

Please specify the principle of the work of asynchronous clear and load in the circuit

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