Develop a Verilog design for a finite state machine $($FSM$)$ controller to manage holiday lights, adhering to the following specifications: $$ Upon activation of the asynchronous $$reset$$ input, the state machine transitions to the idle state. In this state, both the red LED output signal, denoted as $$r$,$ and the green LED output signal, denoted as $$g$,$ are turned off, which means that both LEDs are logic $0$s$.$ When the $$reset$$ input is $1,$ the FSM remains in the idle state. However, when it transitions to logic $0,$ and if the input $$a$$ is logic $1,$ the FSM enters its normal display mode. $$ In the normal display mode, the $$r$$ LED illuminates for one clock cycle, followed by the $$g$$ LED illuminating for two clock cycles. This pattern of alternating between the $$r$$ and $$g$$ LEDs repeats cyclically. However, at any time, the $$r$$ and $$g$$ LEDs will not be on simultaneously. $$ When the $$reset$$ input is logic $0,$ if the input $$a$$ is logic $0,$ both the $$r$$ and $$g$$ LED display patterns will not be changed, and the state machine will stay in the same state. After that, if $$a$$ becomes logic $1,$ both the $$r$$ and $$g$$ LEDs will resume the normal display mode.