Digital Logic question:

Design mixed-logic implementations of the equations for Y and Z in equations (4) and (5) below. The goal in this part is to choose input and output activation levels to minimize the total number gates and chips used in the overall design of these two circuits. Choose only one of the two possible activation-levels for each of the inputs, i.e., A(H), B(L), etc. [but not A(H) for one and A(L) for the other].

(4) Y = /[ (A + /B) * /(C * /D) ]

(5) Z = [ (A*/B) * /(C + D) ]

*******The "/" means not (negation)**********