Draw the state diagram for a state machine that detects the sequence 101 in input x. When it is found the output z=1 should be generated. The machine should generate this output until reset. Inputs are clk, reset, and x, output is z.

a) Draw state diagram

b) What type of machine is this

USING VERILOG IN MODELSIM

c) Write your module statement and define any variables, the module should be named prob3

d) Write the sequential part of the FSM, and be sure to implement a reset

e) Write the combinatorial part of the FSM

f) Write a separate always loop to generate the output z