Exercise $5$

a$)$ Draw the gate level design of a $4-$bit ripple carry adder using the above full adder.

b$)$ What is the critical path of the ripple carry adder? What is the minimum delay considering a

$2-$input XOR takes $2$ns and a $2-$input AND or OR gate takes $1ns$

c$)$ Do the same for a Carry select split in blocks of $2-$bits

d$)$ Construct a $4-$bit carry lookahead adder. Draw the block diagram of the carry lookahead $($you

can use smaller subblocks as black$-$boxes as long as you provide the Boolean expressions

they contain.

e$)$ How does the critical path of a carry$-$lookahead adder increase with regard to the number of

bits added N$?$ How does this compare to the critical path of a ripple carry adder?