Question: Exercise 5.2 Design two adders: a 64-bit ripple-carry adder and a 64-bit carry- lookahead adder with 4-bit blocks. Use only two-input gates. Each two-input gate

Exercise 5.2 Design two adders: a 64-bit ripple-carry adder and a 64-bit carry- lookahead adder with 4-bit blocks. Use only two-input gates. Each two-input gate is 15 pm, has a 50 ps delay, and has 20 ff of total gate capacitance. You may assume that the static power is negligible. (a) Compare the area, delay, and power of the adders (operating at 100 MHz and 1.2 V). (b) Discuss the trade-offs between power, area, and delay

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