FIGURE $4\mathrm{.}23$ The simple control and datapath are extended to handle the unconditional branch instruction. An additional OR$-$gate $($at the upper right$)$ is used to control the multiplexor that chooses between the branch target and the sequential instruction following this one. One input to the OR$-$gate is the Uncondbranch control signal. Although not shown, the Sign$-$extend logic would recognize the unconditional branch opcode and sign$-$extend the lower $26$ bits of the branch instruction to form a $64-$bit address to be added to the PC$.$

$2.$ Consider the following instruction: $0$xB$4150298.$

a$.$ Write this instruction in biriary.

b$.$ Write the instruction in LEGv$8.$

c$.$ What are the outputs of the sign$-$extend and the "shift left $2"$ unit $($near the top of Figure $4\mathrm{.}23)$ for this instruction word in binary and hexadecimal?

d$.$ What is the new PC address after this instruction is executed? Highlight the path through which this value is determined.

e$.$ For each mux, show the values of its inputs and outputs during the execution of this instruction in decimal. List values that are register outputs at Reg $[$X$],$

f$.$ What are the input values for the ALU and the two add units in decimal format?

g$.$ What are the values of all jnputs for the register units in decimal?