Problems in this exercise assume that the logic blocks used to implement a processor's datapath $($COD Figure $4\mathrm{.}23)$ have the following latencies:

"Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. "Register setup" is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File.

$($a$)$ Although the control unit as a whole requires $50$ ps $,$ it so happens that we can extract the correct value of the Reg$2$Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in COD Figure $2\mathrm{.}20($LEGv$8$ instruction encoding$).$ Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR$.$

$($b$)$ What is the latency of an R$-$type instruction $($i$.$e$.,$ how long must the clock period be to ensure that this instruction works correctly$)?$

$($c$)$ What is the latency of LDUR? $($Check your answer carefully. Many students place extra muxes on the critical path.$)$

$($d$)$ What is the latency of STUR? $($Check your answer carefully. Many students place extra muxes on the critical path.$)$

$($e$)$ What is the latency of cBz$?$

$($f$)$ What is the latency of B$?$

$($g$)$ What is the latency of an I$-$type instruction?

$($h$)$ What is the minimum clock period for this CPU? Figure $4\mathrm{.}4\mathrm{.}10$: The simple control and datapath are extended to handle the unconditional branch instruction $($COD Figure $4\mathrm{.}23).$

An additional OR$-$gate $($at the upper right$)$ is used to control the multiplexer that chooses between the branch target and the sequential instruction following this one. One input to the OR$-$gate is the Uncondbranch control signal. Although not shown, the Sign$-$extend logic would recognize the unconditional branch opcode and sign$-$extend the lower $26$ bits of the branch instruction to form a $64-$bit address to be added to the PC$.$