: Following latencies are defined for a processor using multicycle operations.

IF ID EX MEM WB

$200150200350150($in ns$)$

The distribution of instructions is as follows: R$-$Type: $60\%$; LW: $25\%$; SW $15\%$

For a non$-$pipelined sequential operation, determine

$($a$)$ the average thruput

$($b$)$ the average latency

For pipelined operation, determine

$($c$)$ the average thruput

$($d$)$ the average latency