Problem $1[$Pipelining$]$

Each pipeline stage has some latency. Answer the following questions based on a five$-$stage $($IF $->$ ID $->$ EX $->$ MEM $->$ WB $)$ MIPS pipeline. Given below are latencies of the instructions at each stage.

IF ID EX MEM WB

lw $40$ ps $30$ ps $60$ ps $70$ ps $50$ ps

add $40$ ps $30$ ps $90$ ps $10$ ps $50$ ps

addi $40$ ps $20$ ps $90$ ps $5$ ps $50$ ps

sw $40$ ps $30$ ps $70$ ps $70$ ps $70$ ps

$($a$)$ What is the minimum clock cycle time in a single cycle $($non$-$pipelined$)$ processor with these latencies?

$($b$)$ What is the latency of the lw instruction in a single cycle $($non$-$pipelined$)$ processor with these latencies?

$($c$)$ What is the latency of the sw instruction in a single cycle $($non$-$pipelined$)$ processor with these latencies?

$($d$)$ What is the minimum clock cycle time in a pipelined processor with these latencies?

$($e$)$ What is the latency of the lw instruction in a pipelined processor with these latencies?

$($f$)$ What is the latency of the sw instruction in a pipelined processor with these latencies?

$($h$)$ Why do add and addi instructions take longer than the other two in the EX phase?

$($g$)$ Ignoring hazards, how much speed up can you expect in a program with on$-$average $1000$ instructions in a pipelined processor compared to non$-$pipelined operation? You may ignore the decimal points after hundredths $($if the real value is $2\mathrm{.}3333333333,$ you may write $2\mathrm{.}33),$ but you have to be precise about how many clock cycles required for both pipelined and non$-$pipelined processors.

Problem $2[$MCQ$]$

Which of the following type of instructions use Data Memory?

$($a$)$ R$-$type

$($b$)$ Branch

$($c$)$ Load$/$Store