Font Paragraph Styles Figure 4.1 Question 2. Consider the data path shown in Figure 4.2. Assume that the components have the following latencies in picoseconds (R8). Component Mux (each) ALU Add (each) Data memory Instruction memory Registers (read or write) Latency in 20 130 50 200 150 90 What is the cycle time required for each instruction? You must show you work in detail for full credit) a) load b) store 0 Ti 1 + ++ @ & % 5 & 7 0 8 6 $ 4 9 3 2 c) add d) bea e) and I Branch XC Add M Add x AEU operation Data PC Address Instruction Register Registers Register M ALUS Address Zero Data memory Instruction memory RE# Red Data Control Figure 4.2