For a direct-mapped cache address are used to access the cache (shown in the following table). Answer each of the following question: Tag Index Offset a 31-109-5 b 31-12 11-6 5-0 4-0 What is the cache line size (in word) for a)? What is the ratio between total bits required for such a cache implementation over the data storage bits for a)? What is the cache line size (in word) for b)? What is the ratio between total bits required for such a cache implementation over the data storage bits for b)