$]$ Given a CMOS inverter with Vtn $=0\mathrm{.}7$V and Vtp $=-0\mathrm{.}7$V$,$ how would

you modify the widths of the NMOS and PMOS transistors to raise the switching

threshold from $1\mathrm{.}5$V to $2$V$,$ assuming VDD $=3\mathrm{.}3$V$?$

Q$2$: $[7+5+8$ points$]$ Draw the pull$-$up $($i$.$e$.,$ PMOS$)$ network. Y is a function of A$,$ B$,$

C$,$D$,$E$,$F$,$ and G$.$ Write the Boolean Expression of Y$.$ Find the appropriate size of nMOSes

and pMOSes $($hint: compare with equivalent inverter$)$