Given code for a $5-$stage single$-$pipeline microarchitecture $($fetch$,$ decode,

execute, memory, write$-$back$)$

Loop: lw x$1,0($x$2)$

addi x$1,$x$1,1$

sw x$1,0($x$2)$

addi x$2,$x$2,4$

sub x$4,$x$3,$x$2$

bnz x$4,$Loop

All ops are one cycle except LW and SW$,$ which are $1+2$ cycles, and branches,

which are $1+1$ cycles. There is no forwarding.

$1.$ Show the phases of each instruction per clock cycle for one iteration of the loop.

$2.$ How many clock cycles per loop iteration are lost to branch overhead?

$3.$ Assume a static branch predictor, capable of recognizing a backward branch in

the decode stage. Now how many clock cycles are wasted on branch

overhead?

$4.$ Assume a dynamic branch predictor. How many cycles are lost on a correct

prediction?