Given the following truth table, generate the gate level logic circuit, using the $3\mathrm{.}16(50\%)$ Given the following truth table, generate the gate level logic circuit, using the implementation algorithm referred to in Section $3\mathrm{.}3\mathrm{.}4.$

$\backslash$table$[[$A$,$B$,$C$,$Z$],[0,0,0,1],[0,0,1,0],[0,1,0,0],[0,1,1,1],[1,0,0,0],[1,0,1,1],[1,1,0,1],[1,1,1,0]]$

implementation algorithm referred to in Section $3\mathrm{.}3\mathrm{.}4.$