Given the read cycle diagram below, how fast does memory have to be to put its data on the bus at the appropriate time if the bus clock is $178-$MHz and there are $12$ wait states? $($Give your answer in ns to one decimal place.$)$

readcyclebook.jpg

TAD $=2\mathrm{.}1$ ns max

TML $=4\mathrm{.}6$ ns min

TM $=0\mathrm{.}3$ ns max

TRL $=5\mathrm{.}8$ ns max

TDS $=4\mathrm{.}1$ ns min

TMH $=1$ ns max

TRH $=2\mathrm{.}4$ ns max

TDH $=1\mathrm{.}8$ ns min