Q$15.$ Design a high$-$level state machine $($HLSM$)$ that counts the number of $1\text{'}$s in an $8-$bit input A

and outputs the result on a $4-$bit output $C,$ which is initially $0.$ The computation starts when a

single$-$bit input $b$ changes from $0$ to $1.$ The input $b$ becomes $1$ for one clock cycle and then it

returns to $0.$ The computed result should be held at the output until the next time $b$ changes

from $0$ to $1$ and a new value is computed.

$($a$)$ Capture the system behavior as an HLSM and draw the state transition diagram.

$($b$)$ Create a datapath for your HLSM$.$ Label the input$/$output signals of all components.

$($c$)$ Connect the datapath to the controller and show all signals between two units.

$($d$)$ Derive the FSM and draw the state transition diagram.