Question: Hello, In my question there is a 4 inputs AND gate (schematic). It's using 4 input Nand gate for entry and then an inverter. I

Hello,

In my question there is a 4 inputs AND gate (schematic). It's using 4 input Nand gate for entry and then an inverter. I need answer to the following question: 1. give size to each transistor in the schematics if it should be a fastest possible gate to drive a capacitance of 273 units, and a size of the final stage is 64 AND what is gate delay?

Hello, In my question there is a 4 inputs AND gate (schematic).

a G bo [ C C b b ut

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