Help ASAP!

4. (25 pts) We examine how pipelining affects the clock cycle time of the processor Problems in this exercise assume that individual stages of the datapath have the following latencies: IF 250 ps ID EX MEM WB 350 ps 150 ps 300 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows alu (i.e. add, sub,...) beg lw SW 45% 20 % 20 % 15% a. What is the clock cycle time in a pipelined and non-pipelined processor