Help design a BCD2ASCII VHDL CODE. A template is coded blow and instructions on how to fill in the "..." areas is also given

entity BCD2ASCII is port (DS : in STD_LOGIC; RESET:in STD LOGIC FAR CEL: in STD LOGIC LDP: in STD LOGIC RDP: in STD LOGIC: BCD IN: in STD LOGIC VECTOR (7 downto 0) ASCTI OUT: out STD_LOGIC_VECTOR (7 downto 0)) end BCD2ASCII Barchitecture conversion of BCD2ASCII is type ASCII DATA rray (integer range 0 to 7) of STD LOGIC VECTOR a signal SCR DATA ASCII DATA 00100000", "00100000, "00100000", "00100000", "00101110", "00100000") begin with LDP select with RDP select with FAR CEL select ith BCD IN (7 downto 0) select SCR DATA(1)<... scr-data . scr. data with bcd in downto select aprocess reset variable count: integer range to begin if then else and ds end process: conversion>