I keep getting the error [HDL 9-806] Syntax error near "(". even though I think I declared the components correctly. I am using vhdl on vivado 2019. Can someone help with this issue?

-- Declare the required libraries library ieee; use ieee.std_logic_1164.all; use ieee.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; -- use ieee.std_logic_unsigned.all; -- use ieee.std_logic_arith.all;

-- Declare the entity entity functional_unit is

port( -- Declare the enable signal enable_functional_unit: in std_logic_vector(6 downto 0); -- Declare the input signals data_in_1_functional_unit: in std_logic_vector(6 downto 0); data_in_2_functional_unit: in std_logic_vector(6 downto 0); -- Declare the output signal data_out_functional_unit: out std_logic_vector(6 downto 0) ); end entity functional_unit;

-- Describe the architecture architecture structural of functional_unit is

component and_gate_generic( --source of the error enable_and_gate: in std_logic; -- Declare the input signals data_in_1_and_gate: in std_logic_vector(6 downto 0); data_in_2_and_gate: in std_logic_vector(6 downto 0); -- Declare the output signal data_out_and_gate: out std_logic_vector(6 downto 0) ); end component;

component addition( -- Declare the enable signal enable_addition: in std_logic; -- Declare the input signals data_in_1_addition: in std_logic_vector(5 downto 0); data_in_2_addition: in std_logic_vector(5 downto 0); -- Declare the output signal data_out_addition: out std_logic_vector(5 downto 0) ); end component; begin Lu1: and_gate_generic port map( enable_and_gate => enable_functional_unit(0), data_in_1_and_gate => data_in_1_functional_unit, data_in_2_and_gate => data_in_2_functional_unit, data_out_and_gate => data_out_functional_unit ); LU2: addition port map( enable_addition => enable_functional_unit(6), data_in_1_additon => data_in_1_functional_unit, data_in_2_addition => data_in_2_functional_unit, data_out_additon => data_out_functional_unit ); end architecture structural;