I. Objectives The objective of this lab is to construct and analyze synchronous sequential circuits using state table and state transition diagram. II. Preparations 1. Given the sequential circuit below: PRE D1 01 CLK 011 :D DO 00 CLK +CLK QOY F (THE OUTPUT CLR a. Determine whether the circuit above is a Mealy or a Moore machine. b. Construct the state transition table of this state machine. c. Construct the state graph of this state machine. 2. Draw the logic diagram of a 3-bit parallel in parallel out register with mode selection inputs So and Si. The register operates according to the following function table. So 0 0 1 1 Si 0 1 0 1 Register operation No change Complement outputs Clear register to 0 Load parallel data