I will upvote if solved completely

Read Question 1a) 1b) please

(1) Assume the outcome of branch instruction is correctly predicted. (2) Assume there is an integer ALU for address calculation; and another integer ALU for branch and all other integer operations. (3) If the first instruction in an issue packet is a branch instruction, only this branch instruction can be issued in this cycle. (4) Up to two instructions can be committed per cycle. (5) There are two CDBs. (6) For load/store, EX is for address calculation. (7) Only show the first two iterations and ignore the addi instruction before the loop. (8) The functional units (FUs) are pipelined and with latency described in the table below. FU Type Cycles in EX Number of FUS Number of reservation stations 1 2 5 Integer FP adder FP multiplier 12 1 3 18 1 2 Q1-a) With speculation; there are twelve Reorder Buffer (ROB) entries. Q1-b) Without speculation