If I make a mistake, please correct it and give more details

We have a combinatorial logic function that can be decomposed into three steps each with the indicated delay with a resulting clock speed of 2.86 GHz Reg 20ps 105ps 115ps 110ps Assume we further pipeline this logic by adding two additional registers. What would be the resulting clock speed in GHz? 4.25 You can use an expression if you like. Your last answer was interpreted as follows: 4.25 We have a combinatorial logic function that can be decomposed into three steps each with the indicated delay with a resulting clock speed of 4.76 GHz. Reg 20ps 65ps 55ps 70ps Assume we further pipeline this logic by adding just one additional register between the first two or last two stages of combinatorial logic. What would be the highest resulting clock speed we could achieve in GHzi? 6.89