How do you calculate the clock speed? I am completely losc can you go step by step?

We have a combinatorial logic function that can be decomposed into three steps each with the indicated delay with a resulting clock speed of 5.71 GHz. Question 4 Incorrect Reg 20ps 0.00 points out of 1.00 55ps 50ps 50ps P Flag question Assume we further pipeline this logic by adding just one additional register between the first two or last two stages of combinatorial logic. What would be the highest resulting clock speed we could achieve in GHz? 7.14 You can use an expression if you like. Your last answer was interpreted as follows: 7.14 Incorrect answer. Your answer 7.14 is not close enough to the correct answer. If we add the additional register between the first two logic blocks, the delays would be 55 and 100. If we put the register between the 2nd and 3rd block, the delays would be 105 and 50. The best overall delay is thus 100, and the total pipeline delay is 100+20. This results in a clock speed of 8.33 GHz