Question: IM = 2 0 0 adder = 5 0 mux = 2 0 alu = 9 0 regs = 9 0 d - mem =
IMadder mux aluregsdmemsign extend shift left what is the critical time for BEQ and AND instruction for the fill data path if only instructions to implement in a microprocessor architecture are BEQ SW and SLT only then what will be the single clock cycle time based on the values above if propagation time for both sign ext and shift left increase to ps each then find critical time for part I
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